Prakash Ramrakhyani
Prakash Ramrakhyani
Researcher, Arm Inc
Verified email at
Cited by
Cited by
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, JA Joao, MK Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
A case for dynamic pipeline scaling
J Koppanalil, P Ramrakhyani, S Desai, A Vaidyanathan, E Rotenberg
Proceedings of the 2002 international conference on Compilers, architecture …, 2002
Shredder: Learning noise distributions to protect inference privacy
F Mireshghallah, M Taram, P Ramrakhyani, A Jalali, D Tullsen, ...
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
Cache device for coupling to a memory device and a method of operation of such a cache device
NC Paver, SD Biles, D Sunwoo, PS Ramrakhyani
US Patent 8,200,902, 2012
Bbb: Simplifying persistent programming using battery-backed buffers
M Alshboul, P Ramrakhyani, W Wang, J Tuck, Y Solihin
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
Memory organization for security and reliability
G Saileshwar, PS Ramrakhyani, WA Elsasser
US Patent 10,540,297, 2020
Accurate system-level performance modeling and workload characterization for mobile internet devices
M Hayenga, C Sudanthi, M Ghosh, P Ramrakhyani, N Paver
Proceedings of the 9th workshop on MEmory performance: DEaling with …, 2008
Multi-tier cache placement mechanism
J Wang, PS Ramrakhyani, W Wang, WA Elsasser
US Patent 10,831,678, 2020
Shredder: Learning noise to protect privacy with partial DNN inference on the edge
F Mireshghallah, M Taram, P Ramrakhyani, DM Tullsen, H Esmaeilzadeh
CoRR, abs/1905.11814 6, 2019
Retention priority based cache replacement policy
PS Ramrakhyani, AG Saidi
US Patent 9,372,811, 2016
Performing maintenance operations
AL Sandberg, N Nikoleris, PS Ramrakhyani, S Diestelhorst
US Patent 10,929,308, 2021
SESAME: Software defined enclaves to secure inference accelerators with multi-tenant execution
S Banerjee, P Ramrakhyani, S Wei, M Tiwari
arXiv preprint arXiv:2007.06751, 2020
Re-encryption following an OTP update event
AL Sandberg, ML Boettcher, PS Ramrakhyani
US Patent 11,658,808, 2023
Dynamic pipeline scaling
PS Ramrakhyani
Reducing data movement and energy in multilevel cache hierarchies without losing performance: Can you have it all?
J Wang, P Ramrakhyani, W Elsasser, LK John
2019 28th International Conference on Parallel Architectures and Compilation …, 2019
Cache storage for multiple requesters and usage estimation thereof
A Saidi, PS Ramrakhyani
US Patent 11,030,101, 2021
Memory address translation
AL Sandberg, N Nikoleris, PS Ramrakhyani
US Patent 10,831,673, 2020
System, method and apparatus for secure functions and cache line data
AL Sandberg, PS Ramrakhyani
US Patent 10,942,856, 2021
Method and apparatus for control of a tiered memory system
PS Ramrakhyani, J Randall, WA Elsasser
US Patent 10,866,899, 2020
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