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Masatoshi Ishii
Masatoshi Ishii
IBM Research - Tokyo
Verified email at jp.ibm.com
Title
Cited by
Cited by
Year
Neuromorphic computing using non-volatile memory
GW Burr, RM Shelby, A Sebastian, S Kim, S Kim, S Sidler, K Virwani, ...
Advances in Physics: X 2 (1), 89-124, 2017
11712017
1 mb 0.41 Ám▓ 2t-2r cell nonvolatile tcam with two-bit encoding and clocked self-referenced sensing
J Li, RK Montoye, M Ishii, L Chang
IEEE Journal of Solid-State Circuits 49 (4), 896-907, 2013
2342013
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning
S Kim, M Ishii, S Lewis, T Perri, M BrightSky, W Kim, R Jordan, GW Burr, ...
2015 IEEE international electron devices meeting (IEDM), 17.1. 1-17.1. 4, 2015
1942015
Fully on-chip MAC at 14 nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format
P Narayanan, S Ambrogio, A Okazaki, K Hosokawa, H Tsai, A Nomura, ...
IEEE Transactions on Electron Devices 68 (12), 6629-6636, 2021
612021
On-chip trainable 1.4 M 6T2R PCM synaptic array with 1.6 K stochastic LIF neurons for spiking RBM
M Ishii, S Kim, S Lewis, A Okazaki, J Okazawa, M Ito, M Rasch, W Kim, ...
2019 IEEE International Electron Devices Meeting (IEDM), 14.2. 1-14.2. 4, 2019
332019
An analog-AI chip for energy-efficient speech recognition and transcription
S Ambrogio, P Narayanan, A Okazaki, A Fasoli, C Mackin, K Hosokawa, ...
Nature 620 (7975), 768-775, 2023
292023
Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
K Hosokawa, M Ishii, S Kim, CH Lam, SC Lewis
US Patent 10,169,701, 2019
182019
A heterogeneous and programmable compute-in-memory accelerator architecture for analog-AI using dense 2-D mesh
S Jain, H Tsai, CT Chen, R Muralidhar, I Boybat, MM Frank, S Woźniak, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 114-127, 2022
172022
Ultra-low power on-chip learning of speech commands with phase-change memories
VPK Miriyala, M Ishii
arXiv preprint arXiv:2010.11741, 2020
82020
Digital STDP synapse and LIF neuron-based neuromorphic system
T Yasuda, K Hosokawa, Y Nakamura, J Okazawa, M Ishii
US Patent 10,552,731, 2020
82020
Pulse stretching circuit and method
M Ishii, G Yamada, H Miyatake
US Patent US9130548 B2, 2015
72015
Racetrack synapse for neuromorphic applications
MM Frank, JP Han, M Ishii, T Phung, A Pushp
US Patent 10,635,970, 2020
62020
Memory cell structure
K Hosokawa, M Ishii, T Yasuda
US Patent 10,446,231, 2019
62019
Lightweight refresh method for PCM-based neuromorphic circuits
M Ito, M Ishii, A Okazaki, S Kim, J Okazawa, A Nomura, K Hosokawa, ...
2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO), 1-4, 2018
62018
Semiconductor Module, Terminal Strip, Method for Manufacturing Terminal Strip, and Method for Manufacturing Semiconductor Module
M Ishii, Y Yamaji
US Patent App. US 12/707,776, 2010
62010
LUT based neuron membrane potential update scheme in STDP neuromorphic systems
K Hosokawa, M Ishii, Y Nakamura, J Okazawa, T Yasuda
US Patent 10,748,058, 2020
52020
Neuromorphic chip for updating precise synaptic weight values
A Okazaki, M Ishii, J Okazawa, K Hosokawa, T Osogami
US Patent 11,763,139, 2023
42023
Analysis of effect of weight variation on SNN chip with PCM-refresh method
A Nomura, M Ito, A Okazaki, M Ishii, S Kim, J Okazawa, K Hosokawa, ...
Neural Processing Letters 53, 1741-1751, 2021
42021
Timing sequence for digital STDP synapse and LIF neuron-based neuromorphic system
K Hosokawa, M Ishii, Y Nakamura, J Okazawa, T Yasuda
US Patent 11,003,984, 2021
42021
Pattern Training, Inference, and Regeneration Demonstration Using On‐Chip Trainable Neuromorphic Chips for Spiking Restricted Boltzmann Machine
U Shin, M Ishii, A Okazaki, M Ito, MJ Rasch, W Kim, A Nomura, W Choi, ...
Advanced Intelligent Systems 4 (8), 2200034, 2022
32022
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