| Introduction to the Cell multiprocessor JA Kahle, MN Day, HP Hofstee, CR Johns, TR Maeurer, D Shippy IBM journal of Research and Development 49 (4.5), 589-604, 2005 | 1447 | 2005 |
| The design and implementation of a first-generation CELL processor D Pham, S Asano, M Bolliger, MN Day, HP Hofstee, C Johns, J Kahle, ... ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 752 | 2005 |
| Synergistic processing in cell's multicore architecture M Gschwind, HP Hofstee, B Flachs, M Hopkins, Y Watanabe, T Yamazaki IEEE micro 26 (2), 10-24, 2006 | 575 | 2006 |
| Power efficient processor architecture and the Cell processor HP Hofstee 11th International Symposium on High-Performance Computer Architecture, 258-262, 2005 | 556 | 2005 |
| Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor DC Pham, T Aipperspach, D Boerstler, M Bolliger, R Chaudhry, D Cox, ... IEEE journal of solid-state circuits 41 (1), 179-196, 2005 | 333 | 2005 |
| Multi-chip integrated circuit module HP Hofstee, RK Montoye, EJ Sprogis US Patent 6,507,115, 2003 | 309 | 2003 |
| SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode MK Gschwind, HP Hofstee, ME Hopkins US Patent 6,839,828, 2005 | 228 | 2005 |
| Method and system for controlled distribution of application code and content data within a computer network DJ Craft, PK Dubey, HP Hofstee, JA Kahle US Patent 7,603,703, 2009 | 197 | 2009 |
| Cell broadband engine architecture from 20,000 feet HP Hofstee Aug 24 (200), 1-6, 2005 | 130 | 2005 |
| The microarchitecture of the synergistic processor for a cell processor B Flachs, S Asano, SH Dhong, HP Hofstee, G Gervais, R Kim, T Le, P Liu, ... IEEE Journal of Solid-State Circuits 41 (1), 63-70, 2005 | 115 | 2005 |
| Method and system for controlled distribution of application code and content data within a computer network DJ Craft, PK Dubey, HP Hofstee, JA Kahle US Patent 7,650,491, 2010 | 114 | 2010 |
| Communications bus with redundant signal paths and method for compensating for signal path errors in a communications bus SH Dhong, HP Hofstee US Patent 6,982,954, 2006 | 111 | 2006 |
| Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements BC Brock, HP Hofstee, MA Johnson, TW Keller Jr, KJ Nowka US Patent 6,836,849, 2004 | 110 | 2004 |
| Symmetric multi-processing system with attached processing units being able to access a shared memory without being structurally configured with an address translation mechanism ER Altman, PG Capek, M Gschwind, HP Hofstee, JA Kahle, R Nair, ... US Patent 6,779,049, 2004 | 108 | 2004 |
| Computer architecture and software cells for broadband networks M Suzuoki, T Yamazaki, HP Hofstee, ME Hopkins, CR Johns, JA Kahle, ... US Patent 7,233,998, 2007 | 94 | 2007 |
| Multicore processors and systems SW Keckler, HP Hofstee, K Olukotun Springer, 2009 | 88 | 2009 |
| Multiprocessor with pair-wise high reliability mode, and method therefore SH Dhong, HP Hofstee, R Nair, SD Posluszny US Patent 6,772,368, 2004 | 87 | 2004 |
| Processor with redundant logic C Akrout, HP Hofstee, JA Kahle US Patent 6,785,841, 2004 | 81 | 2004 |
| Controlling power and performance in a multiprocessing system B Brock, H Hofstee, M Johnson, T Keller, K Nowka US Patent App. 09/826,986, 2002 | 79 | 2002 |
| In-memory database acceleration on FPGAs: a survey J Fang, YTB Mulder, J Hidders, J Lee, HP Hofstee The VLDB Journal 29, 33-59, 2020 | 73 | 2020 |
