| FinFET scaling to 10 nm gate length B Yu, L Chang, S Ahmed, H Wang, S Bell, CY Yang, C Tabery, C Ho, ... Digest. International Electron Devices Meeting,, 251-254, 2002 | 872 | 2002 |
| Method for forming multiple structures in a semiconductor device B Yu, JX An, CE Tabery, HH Wang US Patent 6,706,571, 2004 | 567 | 2004 |
| Method and apparatus for elimination of bubbles in immersion medium in immersion lithography systems AR Pawloski, AY Abdo, GR Amblard, BM LaFontaine, I Lalovic, ... US Patent 7,014,966, 2006 | 513 | 2006 |
| Method for forming fins in a FinFET device using sacrificial carbon layer MS Buynoski, S Dakshina-Murthy, CE Tabery, HH Wang, CY Yang, B Yu US Patent 6,645,797, 2003 | 209 | 2003 |
| Use of diamond as a hard mask material RJ Huang, PA Fisher, CE Tabery US Patent 6,673,684, 2004 | 178 | 2004 |
| Method of using amorphous carbon as spacer material in a disposable spacer process DE Brown, PA Fisher, RJ Huang, RC Nguyen, CE Tabery US Patent 6,559,017, 2003 | 167 | 2003 |
| Partially de-coupled core and periphery gate module process JP Erhardt, H Kinoshita, C Tabery US Patent 6,835,662, 2004 | 153 | 2004 |
| Use of amorphous carbon for gate patterning PA Fisher, RJ Huang, CE Tabery US Patent 7,015,124, 2006 | 151 | 2006 |
| Method of forming sub-lithographic spaces between polysilicon lines SA Bell, PA Fisher, RC Nguyen, CE Tabery US Patent 6,500,756, 2002 | 129 | 2002 |
| Method for forming multiple fins in a semiconductor device B Yu, JX An, CE Tabery US Patent 6,872,647, 2005 | 115 | 2005 |
| Double and triple gate MOSFET devices and methods for making same MR Lin, JX An, Z Krivokapic, CE Tabery, HH Wang, B Yu US Patent 8,222,680, 2012 | 100 | 2012 |
| Method using planarizing gate material to improve gate critical dimension in semiconductor devices SS Ahmed, CE Tabery, HH Wang, B Yu US Patent 6,787,439, 2004 | 93 | 2004 |
| Method for forming a fin in a finFET device CY Yang, SS Ahmed, S Dakshina-Murthy, CE Tabery, HH Wang, B Yu US Patent 6,787,854, 2004 | 86 | 2004 |
| Disposable hard mask for memory bitline scaling JY Yang, JP Erhardt, C Tabery, W Qian, MT Ramsbey, J Park, T Kamal US Patent 7,018,868, 2006 | 73 | 2006 |
| Gate array with multiple dielectric properties and method for forming same GE William, A Halliyal, MR Lin, M Van Ngo, CE Tabery, CY Yang US Patent 6,563,183, 2003 | 71 | 2003 |
| Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results C Tabery, C Haidinyak, TP Lukanc, L Capodieci, CP Babcock, HE Kim, ... US Patent 7,207,017, 2007 | 65 | 2007 |
| The use of EUV lithography to produce demonstration devices B LaFontaine, Y Deng, RH Kim, HJ Levinson, S McGowan, ... Emerging Lithographic Technologies XII 6921, 212-221, 2008 | 55 | 2008 |
| Finfet gate formation using reverse trim of dummy gate S Dakshina-Murthy, Z Krivokapic, CE Tabery US Patent 6,864,164, 2005 | 53 | 2005 |
| Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes SA Bell, S Dakshina-Murthy, PA Fisher, CE Tabery US Patent 6,664,154, 2003 | 50 | 2003 |
| Planar finFET patterning using amorphous carbon CE Tabery, SA Bell, S Dakshina-Murthy US Patent 6,605,514, 2003 | 47 | 2003 |
