| Silicon nitride etching methods S Panda, R Wise, SD Murthy, K Subramanian US Patent 7,288,482, 2007 | 250 | 2007 |
| Silicon nitride etching methods S Panda, R Wise, SD Murthy, K Subramanian US Patent 7,288,482, 2007 | 250 | 2007 |
| Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing HS Yang, R Malik, S Narasimha, Y Li, R Divakaruni, P Agnello, S Allen, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 234 | 2004 |
| Modeling the synthesis of aluminum particles by evaporation-condensation in an aerosol flow reactor S Panda, SE Pratsinis Nanostructured Materials 5 (7-8), 755-767, 1995 | 164 | 1995 |
| Stressed field effect transistors on hybrid orientation substrate D Chidambarrao, JR Holt, M Ieong, QC Ouyang, S Panda US Patent 7,687,829, 2010 | 114 | 2010 |
| Anisotropic etching of polymer films by high energy (∼ 100s of eV) oxygen atom neutral beams S Panda, DJ Economou, L Chen Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 19 (2 …, 2001 | 110 | 2001 |
| Stressed field effect transistors on hybrid orientation substrate D Chidambarrao, JR Holt, M Ieong, OC Ouyang, S Panda US Patent 7,405,436, 2008 | 107 | 2008 |
| Stressed field effect transistors on hybrid orientation substrate D Chidambarrao, JR Holt, M Ieong, OC Ouyang, S Panda US Patent 7,405,436, 2008 | 107 | 2008 |
| Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies LT Su, J Pellerin, SF Huang, M Khare, D Schepis, K Rim, S Liming, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 93 | 2005 |
| High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
| Effect of metastable oxygen molecules in high density power-modulated oxygen discharges S Panda, DJ Economou, M Meyyappan Journal of Applied Physics 87 (12), 8323-8333, 2000 | 78 | 2000 |
| High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 69 | 2005 |
| Structure and method for making strained channel field effect transistor using sacrificial spacer H Chen, D Chidambarrao, SH Oh, S Panda, WA Rausch, T Sato, ... US Patent 7,135,724, 2006 | 63 | 2006 |
| Structure and method for making strained channel field effect transistor using sacrificial spacer H Chen, D Chidambarrao, SH Oh, S Panda, W Rausch, T Sato, H Utomo US Patent App. 10/711,637, 2006 | 63 | 2006 |
| Method of etching high aspect ratio openings GS Mathad, S Panda, RM Ranade US Patent 6,743,727, 2004 | 60 | 2004 |
| Method of etching high aspect ratio openings G Mathad, S Panda, R Ranade US Patent App. 09/874,109, 2002 | 60 | 2002 |
| Back-Channel Electrolyte-Gated a-IGZO Dual-Gate Thin-Film Transistor for Enhancement of pH Sensitivity Over Nernst Limit N Kumar, J Kumar, S Panda IEEE Electron Device Letters 37 (4), 500-503, 2016 | 58 | 2016 |
| Structure and method for making strained channel field effect transistor using sacrificial spacer H Chen, D Chidambarrao, SH Oh, S Panda, WA Rausch, T Sato, ... US Patent 7,645,656, 2010 | 55 | 2010 |
| Structure and method for making strained channel field effect transistor using sacrificial spacer H Chen, D Chidambarrao, SH Oh, S Panda, W Rausch, T Sato, H Utomo US Patent App. 11/463,777, 2006 | 55* | 2006 |
| Method to increase strain enhancement with spacerless FET and dual liner process HS Yang, S Panda US Patent 7,709,317, 2010 | 51 | 2010 |
