Wu-Tung Cheng

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Yu HuangHiSilicon Co.Verified email at hisilicon.com
Sudhakar ReddyDepartment of ECE, University of IowaVerified email at engineering.uiowa.edu
Dr Manish Dev SharmaProfessor of Physics and Electronics, Panjab University ChandigarhVerified email at pu.ac.in
Janusz RajskiVice President of Engineering, SiemensVerified email at mentor.com
Nilanjan MukherjeeSenior Engineering Director, Siemens Digital Industries SoftwareVerified email at mentor.com
Shi-Yu HuangProfessor of Eletrical Engineering, National Tsing Hua UniversityVerified email at ee.nthu.edu.tw
Liyang LaiCalypto Design SystemsVerified email at mentor.com
Brady BenwareMentor, A Siemens BusinessVerified email at mentor.com
Janak H. PatelElectrical and Computer Engineering, University of Illinois at Urbana-ChampaignVerified email at illinois.edu
Xiaoxin FanDepartment of Electrical and Computer Engineering, University of IowaVerified email at uiowa.edu
Stephen SunterEngineering Director, Mixed-signal DFT, Mentor GraphicsVerified email at mentor.com
Yu Hu (胡瑜)Institute of Computing Technology, Chinese Academy of SciencesVerified email at ict.ac.cn
Bernd BeckerProfessor of Computer Science, University of FreiburgVerified email at informatik.uni-freiburg.de
james C M LiNational Taiwan UniversityVerified email at cc.ee.ntu.edu.tw
Mark M. TehranipoorIntel Charles E. Young Endowed Chair Professor, ECE, University of FloridaVerified email at ufl.edu
Aiman El-MalehProfessor of Computer Engineering, King Fahd University of Petroleum & MineralsVerified email at kfupm.edu.sa

Wu-Tung Cheng

chief scientist, mentor graphics

Verified email at mentor.com

design for test


Title Sort by citations Sort by year Sort by title	Cited by Cited by	Year
PROOFS: A fast, memory-efficient sequential circuit fault simulator TM Niermann, WT Cheng, JH Patel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1992	419	1992
Gentest: an automatic test-generation system for sequential circuits WT Cheng, TJ Chakraborty Computer 22 (4), 43-49, 1989	248	1989
The BACK algorithm for sequential test generation WT Cheng Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 66 …, 1988	244	1988
Optimal core wrapper width selection and SOC test scheduling based on 3-D bin packing algorithm Y Huang, SM Reddy, WT Cheng, P Reuter, N Mukherjee, CC Tsai, ... Proceedings. International Test Conference, 74-82, 2002	213	2002
Resource allocation and test scheduling for concurrent test of core-based SOC design Y Huang, WT Cheng, CC Tsai, N Mukherjee, O Samman, Y Zaidan, ... Proceedings 10th Asian Test Symposium, 265-270, 2001	185	2001
Full-speed bist controller for testing embedded synchronous memories WT Cheng, CJ Hill, O Kebichi US Patent 6,829,728, 2004	119*	2004
Differential fault simulation-A fast method using minimal memory WT Cheng, ML Yu Proceedings of the 26th ACM/IEEE Design Automation Conference, 424-428, 1989	116	1989
Multi-stage test response compactors J Rajski, J Tyszer, G Mrugalski, M Kassab, WT Cheng US Patent 7,818,644, 2010	95	2010
Survey of scan chain diagnosis Y Huang, R Guo, WT Cheng, JCM Li IEEE Design & Test of Computers 25 (3), 240-248, 2008	95	2008
Sequential circuit test generator (STG) benchmark results WT Cheng, S Davidson IEEE International Symposium on Circuits and Systems,, 1939-1941, 1989	93	1989
Diagnosis for wiring interconnects WT Cheng, JL Lewandowski, E Wu Proceedings. International Test Conference 1990, 565-571, 1990	92	1990
Statistical diagnosis for intermittent scan chain hold-time fault Y Huang, WT Cheng, SM Reddy, CJ Hsieh, YT Hung ITC, 319-328, 2003	86	2003
Reduced-pin-count-testing architectures for applying test patterns N Mukherjee, J Jahangiri, R Press, WT Cheng US Patent 7,487,419, 2009	80	2009
X-filter: Filtering unknowns from compacted test responses M Sharma, WT Cheng IEEE International Conference on Test, 2005., 9 pp.-1098, 2005	77	2005
Oscillation-based prebond TSV test LR Huang, SY Huang, S Sunter, KH Tsai, WT Cheng IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013	76	2013
Full-speed field-programmable memory BIST architecture X Du, N Mukherjee, WT Cheng, SM Reddy IEEE International Conference on Test, 2005., 9 pp.-1173, 2005	75	2005
Split circuit model for test generation WT Cheng Annual ACM IEEE Design Automation Conference: Proceedings of the 25 th ACM …, 1988	74	1988
Small delay testing for TSVs in 3-D ICs SY Huang, YH Lin, KH Tsai, WT Cheng, S Sunter, YF Chou, DM Kwai Proceedings of the 49th Annual Design Automation Conference, 1031-1036, 2012	73	2012
Compactor independent direct diagnosis of test hardware Y Huang, WT Cheng, J Rajski US Patent 7,729,884, 2010	69	2010
Signature based diagnosis for logic BIST WT Cheng, M Sharma, T Rinderknecht, L Lai, C Hill 2006 IEEE International Test Conference, 1-9, 2006	68	2006

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