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Sachin Kumawat
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Year
High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule
S Kumawat, R Shrestha, N Daga, R Paily
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (5), 1421-1430, 2015
572015
Regular expression processor and parallel processing architecture
S Kumawat, HK Verma, V Mirian
US Patent 11,449,344, 2022
22022
High-throughput regular expression processing with path priorities using an integrated circuit
DK Liddell, S Kumawat
US Patent 11,983,122, 2024
2024
High-throughput regular expression processing with capture using an integrated circuit
S Kumawat, DK Liddell, PR Schumacher
US Patent 11,861,171, 2024
2024
High-throughput regular expression processing using an integrated circuit
S Kumawat, DK Liddell, W Jiayou
US Patent App. 17/660,801, 2023
2023
CNN agnostic accelerator design for low latency inference on FPGAs
S Kumawat, M Motamedi, S Ghiasi
Hardware Architectures for Deep Learning, 161, 2020
2020
An OpenCL Framework for Real-time Inference of Next-Generation Convolutional Neural Networks on FPGAs
S Kumawat
University of California, Davis, 2017
2017
Multi-Rate Reconfigurable LDPC Decoder Architectures for QC-LDPC codes in High Throughput Applications
S Kumawat
INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI, 2014
2014
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