| High-throughput LDPC-decoder architecture using efficient comparison techniques & dynamic multi-frame processing schedule S Kumawat, R Shrestha, N Daga, R Paily IEEE Transactions on Circuits and Systems I: Regular Papers 62 (5), 1421-1430, 2015 | 51 | 2015 |
| High-throughput regular expression processing with capture using an integrated circuit S Kumawat, DK Liddell, PR Schumacher US Patent 11,816,335, 2023 | | 2023 |
| High-throughput regular expression processing using an integrated circuit S Kumawat, DK Liddell, W Jiayou US Patent App. 17/660,801, 2023 | | 2023 |
| High-throughput regular expression processing with path priorities using an integrated circuit DK Liddell, S Kumawat US Patent App. 17/660,799, 2023 | | 2023 |
| Regular expression processor and parallel processing architecture S Kumawat, HK Verma, V Mirian US Patent 11,449,344, 2022 | | 2022 |
| CNN agnostic accelerator design for low latency inference on FPGAs S Kumawat, M Motamedi, S Ghiasi Hardware Architectures for Deep Learning, 161, 2020 | | 2020 |
| An OpenCL Framework for Real-time Inference of Next-Generation Convolutional Neural Networks on FPGAs S Kumawat University of California, Davis, 2017 | | 2017 |
| Multi-Rate Reconfigurable LDPC Decoder Architectures for QC-LDPC codes in High Throughput Applications S Kumawat INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI, 2014 | | 2014 |
Rahul ShresthaAssociate Professor, IIT MandiVerified email at iitmandi.ac.in
