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Prasanth Chatarasi
Prasanth Chatarasi
Research Staff Member, IBM Research
Verified email at ibm.com - Homepage
Title
Cited by
Cited by
Year
Understanding reuse, performance, and hardware cost of dnn dataflow: A data-centric approach
H Kwon, P Chatarasi, M Pellauer, A Parashar, V Sarkar, T Krishna
Proceedings of the 52nd Annual IEEE/ACM International Symposium on…, 2019
2442019
Maestro: A data-centric approach to understand reuse, performance, and hardware cost of dnn mappings
H Kwon, P Chatarasi, V Sarkar, T Krishna, M Pellauer, A Parashar
IEEE micro 40 (3), 20-29, 2020
1122020
An Extended Polyhedral Model for SPMD programs and its Use in Static Data Race Detection
P Chatarasi, J Shirako, M Kong, V Sarkar
International Workshop on Languages and Compilers for Parallel Computing…, 2016
50*2016
Marvel: a data-centric approach for mapping deep learning operators on spatial accelerators
P Chatarasi, H Kwon, A Parashar, M Pellauer, T Krishna, V Sarkar
ACM Transactions on Architecture and Code Optimization (TACO) 19 (1), 1-26, 2021
46*2021
Polyhedral optimizations of explicitly parallel programs
P Chatarasi, J Shirako, V Sarkar
2015 International Conference on Parallel Architecture and Compilation (PACT…, 2015
41*2015
Evaluating spatial accelerator architectures with tiled matrix-matrix multiplication
GE Moon, H Kwon, G Jeong, P Chatarasi, S Rajamanickam, T Krishna
IEEE Transactions on Parallel and Distributed Systems 33 (4), 1002-1014, 2021
152021
Experimental insights from the rogues gallery
JS Young, J Riedy, TM Conte, V Sarkar, P Chatarasi, S Srikanth
2019 IEEE International Conference on Rebooting Computing (ICRC), 1-8, 2019
122019
Union: A unified HW-SW co-design ecosystem in MLIR for evaluating tensor operations on spatial accelerators
G Jeong, G Kestor, P Chatarasi, A Parashar, PA Tsai, S Rajamanickam, ...
2021 30th International Conference on Parallel Architectures and Compilation…, 2021
112021
Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine
P Chatarasi, S Neuendorffer, S Bayliss, K Vissers, V Sarkar
2020 IEEE High Performance Extreme Computing Conference (HPEC), 1-10, 2020
112020
A preliminary study of compiler transformations for graph applications on the Emu system
P Chatarasi, V Sarkar
Proceedings of the Workshop on Memory Centric High Performance Computing, 37-44, 2018
102018
A unified approach to variable renaming for enhanced vectorization
P Chatarasi, J Shirako, A Cohen, V Sarkar
International Workshop on Languages and Compilers for Parallel Computing, 1-20, 2018
52018
Hardware Abstractions for targeting EDDO Architectures with the Polyhedral Model
A Parashar, P Chatarasi, PA Tsai
IMPACT 2021, 11th International Workshop on Polyhedral Compilation Techniques, 2021
42021
Generation of vector codes for tensor convolutions
SA Neuendorffer, P Chatarasi, SR Bayliss
US Patent 11,422,781, 2022
2022
ADVANCING COMPILER OPTIMIZATIONS FOR GENERAL-PURPOSE & DOMAIN-SPECIFIC PARALLEL ARCHITECTURES
P Chatarasi
Georgia Institute of Technology, 2020
2020
Extending the Polyhedral Compilation Model for Debugging and Optimization of Spmd-Style Explicitly-Parallel Programs
P Chatarasi
Rice University, 2017
2017
2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT)| 978-1-6654-4278-7/21/$31.00 2021 IEEE| DOI: 10.1109/PACT52795. 2021.00033
B Akin, C Angermueller, D Baek, W Baek, CR Banbury, Y Bao, A Basu, ...
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