| Systematic DC/AC performance benchmarking of sub-7-nm node FinFETs and nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek IEEE Journal of the Electron Devices Society 6, 942-947, 2018 | 62 | 2018 |
| Multi- Strategies of 7-nm node Nanosheet FETs With Limited Nanosheet Spacing JS Yoon, J Jeong, S Lee, RH Baek IEEE Journal of the Electron Devices Society 6, 861-865, 2018 | 56 | 2018 |
| Junction design strategy for Si bulk FinFETs for system-on-chip applications down to the 7-nm node JS Yoon, EY Jeong, CK Baek, YR Kim, JH Hong, JS Lee, RH Baek, ... IEEE Electron Device Letters 36 (10), 994-996, 2015 | 43 | 2015 |
| Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths JS Yoon, T Rim, J Kim, M Meyyappan, CK Baek, YH Jeong Applied Physics Letters 105 (10), 2014 | 39 | 2014 |
| An array of metal oxides nanoscale hetero pn junctions toward designable and highly-selective gas sensors H Kwon, JS Yoon, Y Lee, DY Kim, CK Baek, JK Kim Sensors and Actuators B: Chemical 255, 1663-1670, 2018 | 38 | 2018 |
| Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors JS Yoon, T Rim, J Kim, K Kim, CK Baek, YH Jeong Applied Physics Letters 106 (10), 2015 | 37 | 2015 |
| Comprehensive analysis of source and drain recess depth variations on silicon nanosheet FETs for sub 5-nm node SoC application J Jeong, JS Yoon, S Lee, RH Baek IEEE Access 8, 35873-35881, 2020 | 35 | 2020 |
| Investigation of low-frequency noise behavior after hot-carrier stress in an n-channel junctionless nanowire MOSFET CH Park, MD Ko, KH Kim, SH Lee, JS Yoon, JS Lee, YH Jeong IEEE electron device letters 33 (11), 1538-1540, 2012 | 33 | 2012 |
| Device design guideline of 5-nm-node FinFETs and nanosheet FETs for analog/RF applications JS Yoon, RH Baek IEEE Access 8, 189395-189403, 2020 | 31 | 2020 |
| Reduction of process variations for sub-5-nm node fin and nanosheet FETs using novel process scheme JS Yoon, S Lee, J Lee, J Jeong, H Yun, RH Baek IEEE Transactions on Electron Devices 67 (7), 2732-2737, 2020 | 31 | 2020 |
| Performance and variations induced by single interface trap of nanowire FETs at 7-nm node JS Yoon, K Kim, T Rim, CK Baek IEEE Transactions on Electron Devices 64 (2), 339-345, 2016 | 31 | 2016 |
| Sensitivity of source/drain critical dimension variations for sub-5-nm node fin and nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek IEEE Transactions on Electron Devices 67 (1), 258-262, 2019 | 29 | 2019 |
| Bottom oxide bulk FinFETs without punch-through-stopper for extending toward 5-nm node JS Yoon, J Jeong, S Lee, RH Baek IEEE Access 7, 75762-75767, 2019 | 28 | 2019 |
| Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications JS Yoon, J Jeong, S Lee, RH Baek Japanese Journal of Applied Physics 58 (SB), SBBA12, 2019 | 28 | 2019 |
| Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain JS Yoon, J Jeong, S Lee, RH Baek IEEE Access 7, 38593-38596, 2019 | 28 | 2019 |
| Neural approach for modeling and optimizing Si-MOSFET manufacturing HC Choi, H Yun, JS Yoon, RH Baek IEEE Access 8, 159351-159370, 2020 | 26 | 2020 |
| Process-induced variations of 10-nm node bulk nFinFETs considering middle-of-line parasitics JS Yoon, CK Baek, RH Baek IEEE Transactions on Electron Devices 63 (9), 3399-3405, 2016 | 25 | 2016 |
| Metal source-/drain-induced performance boosting of sub-7-nm node nanosheet FETs JS Yoon, J Jeong, S Lee, RH Baek IEEE Transactions on Electron Devices 66 (4), 1868-1873, 2019 | 22 | 2019 |
| Digital/analog performance optimization of vertical nanowire FETs using machine learning JS Yoon, S Lee, H Yun, RH Baek IEEE Access 9, 29071-29077, 2021 | 19 | 2021 |
| Core-shell homojunction silicon vertical nanowire tunneling field-effect transistors JS Yoon, K Kim, CK Baek Scientific reports 7 (1), 41142, 2017 | 19 | 2017 |
Rock-Hyun BaekPOSTECH, Electrical EngineeringVerified email at postech.ac.kr
