| Hardware verification using software analyzers R Mukherjee, D Kroening, T Melham 2015 IEEE Computer Society Annual Symposium on VLSI, 7-12, 2015 | 48 | 2015 |
| Formal Techniques for Effective Co-verification of Hardware/Software Co-designs R Mukherjee, M Purandare, R Polig, D Kroening Design Automation Conference, 35:1--35:6, 2017 | 39 | 2017 |
| v2c–A verilog to C translator R Mukherjee, M Tautschnig, D Kroening Tools and Algorithms for the Construction and Analysis of Systems: 22nd …, 2016 | 19 | 2016 |
| Efficient verification of multi-property designs (The benefit of wrong assumptions) E Goldberg, M Gudemann, D Kroening, R Mukherjee Design, Automation & Test in Europe Conference, DATE, 43--48, 2018 | 15 | 2018 |
| POWER-TRUCTOR: An integrated tool flow for formal verification and coverage of architectural power intent A Hazra, R Mukherjee, P Dasgupta, A Pal, KM Harer, A Banerjee, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2013 | 15 | 2013 |
| Formal verification of hardware/software power management strategies R Mukherjee, P Dasgupta, A Pal, S Mukherjee 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | 15 | 2013 |
| Formal hardware/software co-verification of embedded power controllers P Dasgupta, MK Srivas, R Mukherjee IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014 | 9 | 2014 |
| Equivalence checking using trace partitioning R Mukherjee, D Kroening, T Melham, M Srivas 2015 IEEE Computer Society Annual Symposium on VLSI, 13-18, 2015 | 8 | 2015 |
| Hardware/software co-verification using path-based symbolic execution R Mukherjee, S Joshi, J O'Leary, D Kroening, T Melham arXiv preprint arXiv:2001.01324, 2020 | 6 | 2020 |
| Unbounded safety verification for hardware using software analyzers R Mukherjee, P Schrammel, D Kroening, T Melham 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2016 | 6 | 2016 |
| Operator scheduling revisited: A multi-objective perspective for fine-grained DVS architecture R Mukherjee, P Ghosh, P Dasgupta, A Pal Advances in Computing and Information Technology: Proceedings of the Second …, 2013 | 5 | 2013 |
| Equivalence checking of a floating-point unit against a high-level C model R Mukherjee, S Joshi, A Griesmayer, D Kroening, T Melham FM 2016: Formal Methods: 21st International Symposium, Limassol, Cyprus …, 2016 | 4 | 2016 |
| Lifting CDCL to Template-based Abstract Domains for Program Verification R Mukherjee, P Schrammel, L Haller, D Kroening, T Melham Automated Technology for Verification and Analysis, 2017 | 3 | 2017 |
| A multi-objective perspective for operator scheduling using fine-grained dvs architecture R Mukherjee, P Ghosh, P Dasgupta, A Pal arXiv preprint arXiv:1303.1645, 2013 | 3 | 2013 |
| Multi-objective low-power CDFG scheduling using fine-grained DVS architecture in distributed framework R Mukherjee, P Ghosh, NS Kumar, P Dasgupta, A Pal 2012 International Symposium on Electronic System Design (ISED), 267-271, 2012 | 3 | 2012 |
| HotSpot minimization using fine-grained DVS architecture at 90 nm technology R Mukherjee, P Ghosh, A Pal 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics …, 2012 | 3 | 2012 |
| Equivalence Checking a Floating-point Unit against a High-level C Model (Extended Version) R Mukherjee, S Joshi, A Griesmayer, D Kroening, T Melham arXiv preprint arXiv:1609.00169, 2016 | 2 | 2016 |
| Learning framework for software-hardware model generation and verification R Mukherjee, R Polig, M Purandare US Patent 10,970,449, 2021 | 1 | 2021 |
| Precise abstract interpretation of hardware designs R Mukherjee University of Oxford, 2018 | 1 | 2018 |
| Model checking of global power management strategies in software with temporal logic properties R Mukherjee, S Mukherjee, P Dasgupta Proceedings of the 6th India Software Engineering Conference, 29-34, 2013 | 1 | 2013 |
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