| Efficient link capacity and QoS design for network-on-chip Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 91 | 2006 |
| Network Delays and Link Capacities in Application‐Specific Wormhole NoCs Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny VLSI design 2007 (1), 090941, 2007 | 72 | 2007 |
| Access regulation to hot-modules in wormhole NoCs I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 137-148, 2007 | 51 | 2007 |
| Best of both worlds: A bus enhanced NoC (BENoC) R Manevich, I Cidon, A Kolodny 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 173-182, 2009 | 49 | 2009 |
| A cost effective centralized adaptive routing for networks-on-chip R Manevich, I Cidon, A Kolodny, S Wimer 2011 14th Euromicro Conference on Digital System Design, 39-46, 2011 | 42 | 2011 |
| Centralized adaptive routing for NoCs R Manevich, I Cidon IEEE Computer Architecture Letters 9 (2), 57-60, 2010 | 33 | 2010 |
| Benoc: A bus-enhanced network on-chip for a power efficient CMP I Cidon, A Kolodny IEEE Computer Architecture Letters 7 (2), 61-64, 2008 | 22 | 2008 |
| Leveraging application-level requirements in the design of a NoC for a 4G SoC-a case study R Beraha, I Cidon, A Kolodny 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 17 | 2010 |
| The era of many-modules SoC: revisiting the NoC mapping problem I Walter, I Cidon, A Kolodny, D Sigalov Proceedings of the 2nd International Workshop on Network on Chip …, 2009 | 17 | 2009 |
| Static timing analysis for modeling QoS in networks-on-chip E Krimer, I Keslassy, A Kolodny, M Erez Journal of Parallel and Distributed Computing 71 (5), 687-699, 2011 | 9 | 2011 |
| Capacity optimized NoC for multi-mode SoC I Walter, E Kantor, I Cidon, S Kutten Proceedings of the 48th Design Automation Conference, 942-947, 2011 | 4 | 2011 |
| Packet-level static timing analysis for NoCs E Krimer, M Erez, I Keslassy, A Kolodny 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 88-88, 2009 | 4 | 2009 |
| Spacewire hot modules A Baron, I Walter, I Cidon, R Ginosar, I Keslassy, O Lapid Int. SpaceWire Conf, 2007 | 3 | 2007 |
| Curing Hotspots in Wormhole NoCs AC Isask’har Walter, R Ginosar, A Kolodny DATE, ElectricalEngineering Department, 2006 | 3 | 2006 |
| The design of a latency constrained, power optimized NoC for a 4G SoC R Beraha, I Cidon, A Kolodny Networks-on-Chip, International Symposium on, 86-86, 2009 | 2 | 2009 |
| BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP IC Isask'har Walter, A Kolodny IEEE Computer Architecture Letters 7, 61-64, 2008 | 1 | 2008 |
| A Cost Effective Centralized Adaptive Routing for Networks-on-Chip A Kolodny, I Walter, S Wimer, I Cidon, R Manevich | | 2011 |
| Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study R Beraha, I Walter, I Cidon, A Kolodny Low Power Networks-on-Chip, 175-195, 2011 | | 2011 |
| The Design of a Latency Constrained, Power Optimized NoC for a 4G SoC IC Isask’har Walter, A Kolodny, R Beraha | | 2009 |
| BENoC: A bus-Enhanced Network on-Chip IC Isask'har Walter, A Kolodny | | 2007 |
