Paul V. Gratz

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Steve KecklerVice President of Architecture Research, NVIDIAPatvirtintas el. paštas cs.utexas.edu
Doug BurgerCorporate VP, Managing Director, Microsoft Research CorePatvirtintas el. paštas microsoft.com
Daniel A. JiménezDepartment of Computer Science and Engineering, Texas A&M UniversityPatvirtintas el. paštas acm.org
Jiang HuProfessor of Electrical and Computer Engineering, Texas A&M UniversityPatvirtintas el. paštas tamu.edu
Boris GrotUniversity of EdinburghPatvirtintas el. paštas ed.ac.uk
A. L. Narasimha ReddyTexas A&M UniversityPatvirtintas el. paštas ece.tamu.edu
Gino ChaconAheadComputingPatvirtintas el. paštas aheadcomputing.com
Jinchun KimGPU Performance Engineer, Apple Inc.Patvirtintas el. paštas apple.com
Alex SprintsonProfessor of Electrical and Computer EngineeringPatvirtintas el. paštas tamu.edu
Karthikeyan SankaralingamProfessor of Computer Science, University of Wisconsin-MadisonPatvirtintas el. paštas cs.wisc.edu
Heather L. Hansoncurrently on sabbaticalPatvirtintas el. paštas cedarsagedesign.com
Vassos SoteriouCyprus University of TechnologyPatvirtintas el. paštas cut.ac.cy
Seth H PugsleyResearch Scientist, Intel LabsPatvirtintas el. paštas cs.utah.edu
Kathryn S McKinleyGooglePatvirtintas el. paštas cs.utexas.edu
Mian QinVirtual Machine Monitor team, VMwarePatvirtintas el. paštas tamu.edu
Tushar KrishnaAssociate Professor, Georgia TechPatvirtintas el. paštas ece.gatech.edu
Elvira TeranTexas A&M International UniversityPatvirtintas el. paštas tamiu.edu
LI CHENGvisionICsPatvirtintas el. paštas evisionics.com
Samuel PalermoTexas A&M UniversityPatvirtintas el. paštas ece.tamu.edu
Gwan ChoiTexas A&M UniversityPatvirtintas el. paštas ece.tamu.edu

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Paul V. Gratz

Department of Electrical and Computer Engineering, Texas A&M University

Patvirtintas el. paštas tamu.edu - Pagrindinis puslapis

Computer Architecture Memory Systems Networks on Chip


Pavadinimas Rūšiuoti pagal šaltinius Rūšiuoti pagal metus Rūšiuoti pagal pavadinimą	Cituota Cituota	Metai
Scaling to the End of Silicon with EDGE Architectures D Burger, SW Keckler, KS McKinley, M Dahlin, LK John, C Lin, CR Moore, ... Computer 37 (7), 44-55, 2004	545	2004
Regional congestion awareness for load balance in networks-on-chip P Gratz, B Grot, SW Keckler High Performance Computer Architecture, 2008. HPCA 2008. IEEE 14th …, 2008	501	2008
Implementation and evaluation of on-chip network architectures P Gratz, C Kim, R McDonald, SW Keckler, D Burger Computer Design, 2006. ICCD 2006. International Conference on, 477-484, 2006	258	2006
Distributed microarchitectural protocols in the TRIPS prototype processor K Sankaralingam, R Nagarajan, R McDonald, R Desikan, S Drolia, ... Microarchitecture, 2006. MICRO-39. 39th Annual IEEE/ACM International …, 2006	235	2006
Path confidence based lookahead prefetching J Kim, SH Pugsley, PV Gratz, ALN Reddy, C Wilkerson, Z Chishti 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture …, 2016	193	2016
On-chip interconnection networks of the TRIPS chip P Gratz, C Kim, K Sankaralingam, H Hanson, P Shivakumar, SW Keckler, ... Micro, IEEE 27 (5), 41-50, 2007	149	2007
Perceptron-based prefetch filtering E Bhatia, G Chacon, S Pugsley, E Teran, PV Gratz, DA Jiménez Proceedings of the 46th International Symposium on Computer Architecture, 1-13, 2019	108	2019
GCA: Global congestion awareness for load balance in networks-on-chip M Ramakrishna, VK Kodati, PV Gratz, A Sprintson IEEE Transactions on Parallel and Distributed Systems 27 (7), 2022-2035, 2015	107	2015
LumiNOC: A power-efficient, high-performance, photonic network-on-chip C Li, M Browning, PV Gratz, S Palermo IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014	103*	2014
Running PARSEC 2.1 on M5 M Gebhart, J Hestness, E Fatehi, P Gratz, SW Keckler The University of Texas at Austin, Department of Computer Science, Tech. Rep, 2009	103	2009
An evaluation of the TRIPS computer system M Gebhart, BA Maher, KE Coons, J Diamond, P Gratz, M Marino, ... ACM SIGARCH Computer Architecture News 37 (1), 1-12, 2009	92	2009
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches X Chen, Z Xu, H Kim, P Gratz, J Hu, M Kishinevsky, U Ogras ACM Transactions on Design Automation of Electronic Systems (TODAES) 18 (4 …, 2013	87	2013
Bandwidth-efficient on-chip interconnect designs for GPGPUs H Jang, J Kim, P Gratz, KH Yum, EJ Kim Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015	85	2015
Dynamic voltage and frequency scaling for shared resources in multicore processor designs X Chen, Z Xu, H Kim, PV Gratz, J Hu, M Kishinevsky, U Ogras, R Ayoub Proceedings of the 50th Annual Design Automation Conference, 1-7, 2013	84	2013
Up by their bootstraps: Online learning in artificial neural networks for CMP uncore power management JY Won, X Chen, P Gratz, J Hu, V Soteriou 2014 IEEE 20th International Symposium on High Performance Computer …, 2014	77	2014
Implementation and evaluation of a dynamically routed processor operand network P Gratz, K Sankaralingam, H Hanson, P Shivakumar, R McDonald, ... Proceedings of the First International Symposium on Networks-on-Chip, 7-17, 2007	68	2007
Kill the program counter: Reconstructing program behavior in the processor cache hierarchy J Kim, E Teran, PV Gratz, DA Jiménez, SH Pugsley, C Wilkerson ACM SIGPLAN Notices 52 (4), 737-749, 2017	67	2017
Realistic workload characterization and analysis for networks-on-chip design PV Gratz, SW Keckler The 4th Workshop on Chip Multiprocessor Memory Systems and Interconnects …, 2010	67	2010
METHOD AND APPARATUS FOR CONGESTION-AWARE ROUTING IN A COMPUTER INTERCONNECTION NETWORK P Gratz, B Grot, SW Keckler US Patent App. 20,100/211,718, 2010	65	2010
Use it or lose it: Wear-out and lifetime in future chip multiprocessors H Kim, A Vitkovskiy, PV Gratz, V Soteriou Proceedings of the 46th Annual IEEE/ACM International Symposium on …, 2013	57	2013

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