| Microprocessor software-based self-testing M Psarakis, D Gizopoulos, E Sanchez, MS Reorda IEEE Design & Test of Computers 27 (3), 4-19, 2010 | 344 | 2010 |
| Automatic test program generation: a case study F Corno, E Sánchez, MS Reorda, G Squillero IEEE Design & Test of Computers 21 (2), 102-109, 2004 | 190 | 2004 |
| A reliability analysis of a deep neural network A Bosio, P Bernardi, A Ruospo, E Sanchez 2019 IEEE Latin American Test Symposium (LATS), 1-6, 2019 | 93 | 2019 |
| Development flow for on-line core self-test of automotive microcontrollers P Bernardi, R Cantoro, S De Luca, E Sánchez, A Sansonetti IEEE Transactions on Computers 65 (3), 744-754, 2015 | 92 | 2015 |
| Evolutionary Optimization: the μGP toolkit E Sanchez, M Schillaci, G Squillero Springer Science & Business Media, 2011 | 87 | 2011 |
| Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation S Di Carlo, M Falasconi, E Sánchez, A Scionti, G Squillero, A Tonda Pattern Recognition Letters 32 (13), 1594-1603, 2011 | 61 | 2011 |
| Evolving assembly programs: how games help microprocessor validation F Corno, E Sánchez, G Squillero IEEE Transactions on Evolutionary Computation 9 (6), 695-706, 2005 | 60 | 2005 |
| Towards automated malware creation: code generation and code integration A Cani, M Gaudesi, E Sanchez, G Squillero, A Tonda Proceedings of the 29th annual ACM symposium on applied computing, 157-160, 2014 | 52 | 2014 |
| Investigating data representation for efficient and reliable convolutional neural networks A Ruospo, E Sanchez, M Traiola, I O’connor, A Bosio Microprocessors and Microsystems 86, 104318, 2021 | 47 | 2021 |
| On-line functionally untestable fault identification in embedded processor cores P Bernardi, M Bonazza, E Sánchez, MS Reorda, O Ballan 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013 | 40 | 2013 |
| Evaluating convolutional neural networks reliability depending on their data representation A Ruospo, A Bosio, A Ianne, E Sanchez 2020 23rd Euromicro Conference on Digital System Design (DSD), 672-679, 2020 | 38 | 2020 |
| Fault grading of software-based self-test procedures for dependable automotive applications P Bernardi, M Grosso, E Sánchez, O Ballan 2011 Design, Automation & Test in Europe, 1-2, 2011 | 36 | 2011 |
| An effective technique for the automatic generation of diagnosis-oriented programs for processor cores P Bernardi, EES Sánchez, M Schillaci, G Squillero, MS Reorda IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2008 | 36 | 2008 |
| A functional power evaluation flow for defining test power limits during at-speed delay testing M Valka, A Bosio, L Dilillo, P Girard, S Pravossoudovitch, A Virazel, ... 2011 Sixteenth IEEE European Test Symposium, 153-158, 2011 | 35 | 2011 |
| A pipelined multi-level fault injector for deep neural networks A Ruospo, A Balaara, A Bosio, E Sanchez 2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2020 | 34 | 2020 |
| On the functional test of branch prediction units E Sanchez, MS Reorda IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23 (9 …, 2014 | 33 | 2014 |
| Industrial applications of evolutionary algorithms E Sanchez, G Squillero, A Tonda Springer Berlin Heidelberg, 2012 | 32 | 2012 |
| An effective technique for minimizing the cost of processor software-based diagnosis in SoCs P Bernardi, E Sánchez, M Schillaci, G Squillero, MS Reorda Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 32 | 2006 |
| On the in-field functional testing of decode units in pipelined RISC processors P Bernardi, R Cantoro, L Ciganda, E Sánchez, MS Reorda, S De Luca, ... 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and …, 2014 | 31 | 2014 |
| On-line software-based self-test of the address calculation unit in RISC processors P Bernardi, L Ciganda, M de Carvalho, M Grosso, J Lagos-Benites, ... 2012 17th IEEE European Test Symposium (ETS), 1-6, 2012 | 31 | 2012 |
Matteo SONZA REORDAPolitecnico di Torino, Dept. of Control and Computer EngineeringVerified email at polito.it
