| Shared last-level TLBs for chip multiprocessors A Bhattacharjee, D Lustig, M Martonosi 2011 IEEE 17th International Symposium on High Performance Computer …, 2011 | 185 | 2011 |
| Triggered instructions: A control paradigm for spatially-programmed architectures A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ... ACM SIGARCH Computer Architecture News 41 (3), 142-153, 2013 | 147 | 2013 |
| Reducing GPU offload latency via fine-grained CPU-GPU synchronization D Lustig, M Martonosi 2013 IEEE 19th International Symposium on High Performance Computer …, 2013 | 146 | 2013 |
| Nimble page management for tiered memory systems Z Yan, D Lustig, D Nellans, A Bhattacharjee Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 109 | 2019 |
| TLB improvements for chip multiprocessors: Inter-core cooperative prefetchers and shared last-level TLBs D Lustig, A Bhattacharjee, M Martonosi ACM Transactions on Architecture and Code Optimization (TACO) 10 (1), 1-38, 2013 | 87 | 2013 |
| PipeCheck: Specifying and verifying microarchitectural enforcement of memory consistency models D Lustig, M Pellauer, M Martonosi 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 635-646, 2014 | 75 | 2014 |
| MeltdownPrime and SpectrePrime: Automatically-synthesized attacks exploiting invalidation-based coherence protocols C Trippel, D Lustig, M Martonosi arXiv preprint arXiv:1802.03802, 2018 | 71 | 2018 |
| Checkmate: Automated synthesis of hardware exploits and security litmus tests C Trippel, D Lustig, M Martonosi 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 68 | 2018 |
| TriCheck: Memory model verification at the trisection of software, hardware, and ISA C Trippel, YA Manerkar, D Lustig, M Pellauer, M Martonosi ACM SIGPLAN Notices 52 (4), 119-133, 2017 | 62 | 2017 |
| COATCheck: Verifying memory ordering at the hardware-OS interface D Lustig, G Sethi, M Martonosi, A Bhattacharjee ACM SIGPLAN Notices 51 (4), 233-247, 2016 | 58 | 2016 |
| Translation ranger: Operating system support for contiguity-aware tlbs Z Yan, D Lustig, D Nellans, A Bhattacharjee Proceedings of the 46th International Symposium on Computer Architecture …, 2019 | 52 | 2019 |
| A formal analysis of the NVIDIA PTX memory consistency model D Lustig, S Sahasrabuddhe, O Giroux Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019 | 51 | 2019 |
| Automated synthesis of comprehensive memory model litmus test suites D Lustig, A Wright, A Papakonstantinou, O Giroux ACM SIGPLAN Notices 52 (4), 661-675, 2017 | 51 | 2017 |
| CCICheck: Using µhb graphs to verify the coherence-consistency interface YA Manerkar, D Lustig, M Pellauer, M Martonosi Proceedings of the 48th International Symposium on Microarchitecture, 26-37, 2015 | 51 | 2015 |
| Efficient control and communication paradigms for coarse-grained spatial architectures M Pellauer, A Parashar, M Adler, B Ahsan, R Allmon, N Crago, K Fleming, ... ACM Transactions on Computer Systems (TOCS) 33 (3), 1-32, 2015 | 50 | 2015 |
| Efficient spatial processing element control via triggered instructions A Parashar, M Pellauer, M Adler, B Ahsan, N Crago, D Lustig, V Pavlov, ... IEEE Micro 34 (3), 120-137, 2014 | 48 | 2014 |
| ArMOR: Defending against memory consistency model mismatches in heterogeneous architectures D Lustig, C Trippel, M Pellauer, M Martonosi Proceedings of the 42nd Annual International Symposium on Computer …, 2015 | 46 | 2015 |
| RTLCheck: Verifying the memory consistency of RTL designs YA Manerkar, D Lustig, M Martonosi, M Pellauer Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 39 | 2017 |
| Architectural and operating system support for virtual memory A Bhattacharjee, D Lustig, M Martonosi Morgan & Claypool, 2018 | 37 | 2018 |
| Hmg: Extending cache coherence protocols across modern hierarchical multi-gpu systems X Ren, D Lustig, E Bolotin, A Jaleel, O Villa, D Nellans 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 30 | 2020 |
