| Single-event transient in FinFETs and nanosheet FETs J Kim, JS Lee, JW Han, M Meyyappan IEEE Electron Device Letters 39 (12), 1840-1843, 2018 | 52 | 2018 |
| Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths JS Yoon, T Rim, J Kim, M Meyyappan, CK Baek, YH Jeong Applied Physics Letters 105 (10), 2014 | 39 | 2014 |
| Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors JS Yoon, T Rim, J Kim, K Kim, CK Baek, YH Jeong Applied Physics Letters 106 (10), 2015 | 36 | 2015 |
| Design guidelines for nanoscale vacuum field emission transistors J Kim, J Kim, H Oh, M Meyyappan, JW Han, JS Lee Journal of Vacuum Science & Technology B 34 (4), 2016 | 28 | 2016 |
| Nanoscale complementary vacuum field emission transistor JW Han, ML Seol, J Kim, M Meyyappan ACS Applied Nano Materials 3 (11), 11481-11488, 2020 | 22 | 2020 |
| Caution: Abnormal variability due to terrestrial cosmic rays in scaled-down FinFETs J Kim, JS Lee, JW Han, M Meyyappan IEEE Transactions on Electron Devices 66 (4), 1887-1891, 2019 | 22 | 2019 |
| Improved performance of In2Se3 nanowire phase-change memory with SiO2 passivation CK Baek, D Kang, JS Kim, B Jin, T Rim, S Park, M Meyyappan, YH Jeong, ... Solid-state electronics 80, 10-13, 2013 | 22 | 2013 |
| Reduction of variability in junctionless and inversion-mode FinFETs by stringer gate structure J Kim, JW Han, M Meyyappan IEEE Transactions on Electron Devices 65 (2), 470-475, 2018 | 21 | 2018 |
| Thermally efficient and highly scalable In2Se3 nanowire phase change memory B Jin, D Kang, J Kim, M Meyyappan, JS Lee Journal of Applied Physics 113 (16), 2013 | 20 | 2013 |
| Surround gate transistor with epitaxially grown Si pillar and simulation study on soft error and rowhammer tolerance for DRAM JW Han, J Kim, D Beery, KD Bozdag, P Cuevas, A Levi, I Tain, K Tran, ... IEEE Transactions on Electron Devices 68 (2), 529-534, 2021 | 15 | 2021 |
| Effects of single grain boundary and random interface traps on electrical variations of sub-30 nm polysilicon nanowire structures H Oh, J Kim, J Lee, T Rim, CK Baek, JS Lee Microelectronic Engineering 149, 113-116, 2016 | 14 | 2016 |
| Soft error in saddle fin based DRAM JW Han, J Kim, DI Moon, JS Lee, M Meyyappan IEEE Electron Device Letters 40 (4), 494-497, 2019 | 13 | 2019 |
| Threshold voltage variations due to oblique single grain boundary in sub-50-nm polysilicon channel J Kim, T Rim, J Lee, CK Baek, M Meyyappan, JS Lee IEEE Transactions on Electron Devices 61 (8), 2705-2710, 2014 | 11 | 2014 |
| The impact of a single displacement defect on tunneling field-effect transistors J Kim, JW Han, M Meyyappan IEEE Transactions on Electron Devices 67 (11), 4765-4769, 2020 | 9 | 2020 |
| Work function consideration in vacuum field emission transistor design J Kim, H Oh, J Kim, RH Baek, JW Han, M Meyyappan, JS Lee Journal of Vacuum Science & Technology B 35 (6), 2017 | 9 | 2017 |
| Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness J Kim, H Oh, J Kim, M Meyyappan, JS Lee Japanese Journal of Applied Physics 56 (2), 024201, 2017 | 5 | 2017 |
| Three-dimensional simulation of threshold voltage variations due to an oblique single grain boundary in sub-40 nm polysilicon nanowire FETs J Kim, H Oh, J Lee, CK Baek, M Meyyappan, JS Lee Semiconductor Science and Technology 30 (8), 085015, 2015 | 5 | 2015 |
| The Impact of Displacement Defect in Nanosheet Field Effect Transistor J Kim Journal of Electrical Engineering & Technology 16 (1), 525-529, 2021 | 3 | 2021 |
| Transformable Junctionless Transistor (T-JLT) JW Han, J Kim, M Meyyappan IEEE Transactions on Electron Devices 67 (6), 2639-2644, 2020 | 1 | 2020 |
Jin-Woo HanResearch ScientistVerified email at nasa.gov
