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Konstantin Moiseev
Konstantin Moiseev
Doctor of Electrical Engineering, Intel Israel
Verified email at intel.com
Title
Cited by
Cited by
Year
Timing-aware power-optimal ordering of signals
K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (4 …, 2008
382008
Optimal bus sizing in migration of processor design
S Wimer, S Michaely, K Moiseev, A Kolodny
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (5), 1089-1100, 2006
202006
Power-delay optimization in vlsi microprocessors by wire spacing
K Moiseev, A Kolodny, S Wimer
ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (4 …, 2009
182009
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing
K Moiseev, S Wimer, A Kolodny
2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006
152006
On optimal ordering of signals in parallel wire bundles
K Moiseev, S Wimer, A Kolodny
Integration 41 (2), 253-268, 2008
142008
Multi-Net Optimization of VLSI Interconnect
K Moiseev, A Kolodny, S Wimer
Springer, 2015
122015
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing
K Moiseev, S Wimer, A Kolodny
Integration 48, 116-128, 2015
82015
Interconnect bundle sizing under discrete design rules
K Moiseev, A Kolodny, S Wimer
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010
42010
Author's accepted manuscript
R Mishra, S Sharma, RS Sharma, S Singh, MM Sardesai, S Sharma
J Ethnopharmacol, 2018
32018
An Overview of the VLSI Interconnect Problem
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 1-9, 2015
32015
On VLSI interconnect optimization and linear ordering problem
S Wimer, K Moiseev, A Kolodny
Optimization and Engineering 12, 603-609, 2011
32011
The complexity of VLSI power-delay optimization by interconnect resizing
K Moiseev, A Kolodny, S Wimer
Journal of combinatorial optimization 23, 292-300, 2012
22012
Dynamic programming algorithm for interconnect channel sizing in discrete design rules
K Moiseev, S Wimer, A Kolodny
CCIT report 730, 2009
12009
Frameworks for Interconnect Optimization
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 35-42, 2015
2015
Scaling Dependent Electrical Modeling of Interconnects
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 17-34, 2015
2015
Interconnect Aspects in Design Methodology and EDA Tools
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 11-16, 2015
2015
Interconnect Optimization by Net Ordering
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 167-194, 2015
2015
Net-by-Net Wire Optimization
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 43-61, 2015
2015
Multi-net Sizing and Spacing in General Layouts
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 107-165, 2015
2015
Multi-net Sizing and Spacing of Bundle Wires
K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer
Multi-Net Optimization of VLSI Interconnect, 63-106, 2015
2015
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Articles 1–20