| Timing-aware power-optimal ordering of signals K Moiseev, A Kolodny, S Wimer ACM Transactions on Design Automation of Electronic Systems (TODAES) 13 (4 …, 2008 | 35 | 2008 |
| Optimal bus sizing in migration of processor design S Wimer, S Michaely, K Moiseev, A Kolodny IEEE Transactions on Circuits and Systems I: Regular Papers 53 (5), 1089-1100, 2006 | 20 | 2006 |
| Power-delay optimization in vlsi microprocessors by wire spacing K Moiseev, A Kolodny, S Wimer ACM Transactions on Design Automation of Electronic Systems (TODAES) 14 (4 …, 2009 | 18 | 2009 |
| On optimal ordering of signals in parallel wire bundles K Moiseev, S Wimer, A Kolodny Integration 41 (2), 253-268, 2008 | 14 | 2008 |
| Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing K Moiseev, S Wimer, A Kolodny 2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006 | 14 | 2006 |
| Multi-Net Optimization of VLSI Interconnect K Moiseev, A Kolodny, S Wimer Springer, 2015 | 12 | 2015 |
| Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing K Moiseev, S Wimer, A Kolodny Integration 48, 116-128, 2015 | 8 | 2015 |
| „Author‟ s Accepted Manuscript‟ S Moreira, S Meireles, T Brandão, PG de Pinho Journal of Ethnopharmacology, 2018 | 4 | 2018 |
| On VLSI interconnect optimization and linear ordering problem S Wimer, K Moiseev, A Kolodny Optimization and Engineering 12, 603-609, 2011 | 4 | 2011 |
| Interconnect bundle sizing under discrete design rules K Moiseev, A Kolodny, S Wimer IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2010 | 4 | 2010 |
| An overview of the vlsi interconnect problem K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 1-9, 2015 | 2 | 2015 |
| The complexity of VLSI power-delay optimization by interconnect resizing K Moiseev, A Kolodny, S Wimer Journal of combinatorial optimization 23, 292-300, 2012 | 2 | 2012 |
| Interconnect Optimization by Net Ordering K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 167-194, 2015 | 1 | 2015 |
| Dynamic programming algorithm for interconnect channel sizing in discrete design rules K Moiseev, S Wimer, A Kolodny CCIT report 730, 2009 | 1 | 2009 |
| Frameworks for Interconnect Optimization K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 35-42, 2015 | | 2015 |
| Scaling Dependent Electrical Modeling of Interconnects K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 17-34, 2015 | | 2015 |
| Interconnect Aspects in Design Methodology and EDA Tools K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 11-16, 2015 | | 2015 |
| Net-by-Net Wire Optimization K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 43-61, 2015 | | 2015 |
| Multi-net Sizing and Spacing in General Layouts K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 107-165, 2015 | | 2015 |
| Multi-net Sizing and Spacing of Bundle Wires K Moiseev, A Kolodny, S Wimer, K Moiseev, A Kolodny, S Wimer Multi-Net Optimization of VLSI Interconnect, 63-106, 2015 | | 2015 |
Avinoam KolodnyProfessor of Electrical and Computer Engineering, TechnionVerified email at ee.technion.ac.il
