kohji hosokawa
kohji hosokawa
IBM Research Tokyo
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A 5.3 GHz 8T-SRAM with operation down to 0.41 V in 65nm CMOS
L Chang, Y Nakamura, RK Montoye, J Sawada, AK Martin, K Kinoshita, ...
2007 IEEE Symposium on VLSI Circuits, 252-253, 2007
NVM neuromorphic core with 64k-cell (256-by-256) phase change memory synaptic array with on-chip neuron circuits for continuous in-situ learning
S Kim, M Ishii, S Lewis, T Perri, M BrightSky, W Kim, R Jordan, GW Burr, ...
2015 IEEE international electron devices meeting (IEDM), 17.1. 1-17.1. 4, 2015
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory
P Narayanan, A Fumarola, LL Sanches, K Hosokawa, SC Lewis, ...
IBM Journal of Research and Development 61 (4/5), 11: 1-11: 11, 2017
Fully on-chip MAC at 14 nm enabled by accurate row-wise programming of PCM-based weights and parallel vector-transport in duration-format
P Narayanan, S Ambrogio, A Okazaki, K Hosokawa, H Tsai, A Nomura, ...
IEEE Transactions on Electron Devices 68 (12), 6629-6636, 2021
Vibrations of clamped orthotropic rectangular plates
T Sakata, K Hosokawa
Journal of Sound and Vibration 125 (3), 429-439, 1988
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed
HY Chang, P Narayanan, SC Lewis, NCP Farinha, K Hosokawa, ...
IBM Journal of Research and Development 63 (6), 8: 1-8: 14, 2019
On-chip trainable 1.4 M 6T2R PCM synaptic array with 1.6 K stochastic LIF neurons for spiking RBM
M Ishii, S Kim, S Lewis, A Okazaki, J Okazawa, M Ito, M Rasch, W Kim, ...
2019 IEEE International Electron Devices Meeting (IEDM), 14.2. 1-14.2. 4, 2019
An analog-AI chip for energy-efficient speech recognition and transcription
S Ambrogio, P Narayanan, A Okazaki, A Fasoli, C Mackin, K Hosokawa, ...
Nature 620 (7975), 768-775, 2023
DRAM with multiple virtual bank architecture for random row access
K Hosokawa, T Sunaga, S Watanabe
US Patent 6,925,028, 2005
An eight-bit prefetch circuit for high-bandwidth DRAM's
T Sunaga, K Hosokawa, Y Nakamura, M Ichinose, Y Igarashi
IEEE Journal of Solid-State Circuits 32 (1), 105-110, 1997
Free vibrations of clamped symmetrically laminated skew plates
K Hosokawa, Y Terada, T Sakata
Journal of sound and vibration 189 (4), 525-533, 1996
A full bit prefetch architecture for synchronous DRAM's
T Sunaga, K Hosokawa, Y Nakamura, M Ichinose, A Moriwaki, S Kakimi, ...
IEEE Journal of Solid-State Circuits 30 (9), 998-1005, 1995
A 14-ns 14-Mb CMOS DRAM with 300-mW active power
T Kirihata, SH Dhong, K Kitamura, T Sunaga, Y Katayama, ...
IEEE journal of solid-state circuits 27 (9), 1222-1228, 1992
Dram array with local latches
T Sunaga, K Hosokawa
US Patent 5,732,042, 1998
A heterogeneous and programmable compute-in-memory accelerator architecture for analog-AI using dense 2-D mesh
S Jain, H Tsai, CT Chen, R Muralidhar, I Boybat, MM Frank, S Woźniak, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 31 (1), 114-127, 2022
A 220-mm/sup 2/, four-and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture
T Kirihata, M Gall, K Hosokawa, JM Dortu, H Wong, P Pfefferi, BL Ji, ...
IEEE Journal of Solid-State Circuits 33 (11), 1711-1719, 1998
Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
K Hosokawa, M Ishii, S Kim, CH Lam, SC Lewis
US Patent 10,572,799, 2020
Communicating postsynaptic neuron fires to neuromorphic cores
K Hosokawa, S Kim, CH Lam
US Patent 10,417,559, 2019
A double-data-rate 2 (DDR2) interface phase-change memory with 533MB/s read-write data rate and 37.5 ns access latency for memory-type storage class memory applications
HL Lung, CP Miller, CJ Chen, SC Lewis, J Morrish, T Perri, RC Jordan, ...
2016 IEEE 8th International Memory Workshop (IMW), 1-5, 2016
Unassisted true analog neural network training chip
Y Kohda, Y Li, K Hosokawa, S Kim, R Khaddam-Aljameh, Z Ren, ...
2020 IEEE International Electron Devices Meeting (IEDM), 36.2. 1-36.2. 4, 2020
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