| QNoC: QoS architecture and design process for network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Journal of systems architecture 50 (2-3), 105-128, 2004 | 813 | 2004 |
| MCM-GPU: Multi-chip-module GPUs for continued performance scalability A Arunkumar, E Bolotin, B Cho, U Milic, E Ebrahimi, O Villa, A Jaleel, ... ACM SIGARCH Computer Architecture News 45 (2), 320-332, 2017 | 209 | 2017 |
| Scaling the power wall: a path to exascale O Villa, DR Johnson, M Oconnor, E Bolotin, D Nellans, J Luitjens, ... SC'14: Proceedings of the International Conference for High Performance …, 2014 | 157 | 2014 |
| Many-core vs. many-thread machines: Stay away from the valley Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser IEEE Computer Architecture Letters 8 (1), 25-28, 2009 | 141 | 2009 |
| Cost considerations in network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Integration 38 (1), 19-42, 2004 | 138 | 2004 |
| The power of priority: NoC based distributed cache coherency E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007 | 106 | 2007 |
| Anatomy of gpu memory system for multi-application execution A Jog, O Kayiran, T Kesten, A Pattnaik, E Bolotin, N Chatterjee, ... Proceedings of the 2015 International Symposium on Memory Systems, 223-234, 2015 | 101 | 2015 |
| Routing table minimization for irregular mesh NoCs E Bolotin, I Cidon, R Ginosar, A Kolodny 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 94 | 2007 |
| Efficient link capacity and QoS design for network-on-chip Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 90 | 2006 |
| A case for toggle-aware compression for GPU systems G Pekhimenko, E Bolotin, N Vijaykumar, O Mutlu, TC Mowry, SW Keckler 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 85 | 2016 |
| Beyond the socket: NUMA-aware GPUs U Milic, O Villa, E Bolotin, A Arunkumar, E Ebrahimi, A Jaleel, A Ramirez, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 80 | 2017 |
| Application-aware memory system for fair and efficient execution of concurrent gpgpu applications A Jog, E Bolotin, Z Guz, M Parker, SW Keckler, MT Kandemir, CR Das Proceedings of workshop on general purpose processing using GPUs, 1-8, 2014 | 78 | 2014 |
| Network delays and link capacities in application-specific wormhole NoCs Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny VLSI design 2007, 2007 | 72 | 2007 |
| Automatic hardware-efficient SoC integration by QoS network on chip E Bolotin, A Morgenshtein, I Cidon, R Ginosar, A Kolodny Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004 | 61 | 2004 |
| Combining HW/SW mechanisms to improve NUMA performance of multi-GPU systems V Young, A Jaleel, E Bolotin, E Ebrahimi, D Nellans, O Villa 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 55 | 2018 |
| Understanding the future of energy efficiency in multi-module gpus A Arunkumar, E Bolotin, D Nellans, CJ Wu 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 34 | 2019 |
| Hmg: Extending cache coherence protocols across modern hierarchical multi-gpu systems X Ren, D Lustig, E Bolotin, A Jaleel, O Villa, D Nellans 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 30 | 2020 |
| Hybrid exclusive multi-level memory architecture with memory management DG Feekes, S Raikin, B Fanning, J Ray, J Mandelblat, A Berkovits, ... US Patent 9,734,079, 2017 | 30 | 2017 |
| Toggle-aware compression for GPUs G Pekhimenko, E Bolotin, M O’Connor, O Mutlu, TC Mowry, SW Keckler IEEE Computer Architecture Letters 14 (2), 164-168, 2015 | 28 | 2015 |
| Designing efficient heterogeneous memory architectures E Bolotin, D Nellans, O Villa, M O'Connor, A Ramirez, SW Keckler IEEE Micro 35 (4), 60-68, 2015 | 23 | 2015 |
Avinoam KolodnyProfessor of Electrical and Computer Engineering, TechnionVerified email at ee.technion.ac.il
