Gururaj Saileshwar
Cited by
Cited by
Cleanupspec: An" undo" approach to safe speculation
G Saileshwar, MK Qureshi
52nd Annual IEEE/ACM International Symposium on Microarchitecture, 73-86, 2019
Morphable counters: Enabling compact integrity trees for low-overhead secure memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, JA Joao, MK Qureshi
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Synergy: Rethinking secure-memory design for error-correcting memories
G Saileshwar, PJ Nair, P Ramrakhyani, W Elsasser, MK Qureshi
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
G Saileshwar, M Qureshi
30th USENIX Security Symposium (USENIX Security 21), 2021
Streamline: a fast, flushless cache covert-channel attack by enabling asynchronous collusion
G Saileshwar, CW Fletcher, M Qureshi
26th ACM International Conference on Architectural Support for Programming …, 2021
Randomized row-swap: mitigating row hammer by breaking spatial correlation between aggressor and victim rows
G Saileshwar, B Wang, M Qureshi, PJ Nair
Proceedings of the 27th ACM International Conference on Architectural …, 2022
Hydra: Enabling low-overhead mitigation of row-hammer at ultra-low thresholds via hybrid tracking
M Qureshi, A Rohan, G Saileshwar, PJ Nair
Proceedings of the 49th Annual International Symposium on Computer …, 2022
Memory organization for security and reliability
G Saileshwar, PS Ramrakhyani, WA Elsasser
US Patent 10,540,297, 2020
AQUA: Scalable Rowhammer Mitigation by Quarantining Aggressor Rows at Runtime
A Saxena, G Saileshwar, PJ Nair, M Qureshi
2022 55th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), 2022
Scalable and Secure Row-Swap: Efficient and Safe Row Hammer Mitigation in Memory Systems
J Woo, G Saileshwar, PJ Nair
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
Heapcheck: Low-cost hardware support for memory safety
G Saileshwar, R Boivie, T Chen, B Segal, A Buyuktosunoglu
ACM Transactions on Architecture and Code Optimization (TACO) 19 (1), 1-24, 2022
Bespoke Cache Enclaves: Fine-Grained and Scalable Isolation from Cache Side-Channels via Flexible Set-Partitioning
G Saileshwar, S Kariyappa, M Qureshi
IEEE International Symposium on Secure and Private Execution Environment …, 2021
Lookout for zombies: Mitigating flush+ reload attack on shared caches by monitoring invalidated lines
G Saileshwar, MK Qureshi
arXiv preprint arXiv:1906.02362, 2019
CMOS low-noise signal conditioning with a novel differential “resistance to frequency” converter for resistive sensor applications
P Kabara, S Thakur, G Saileshwar, MS Baghini, DK Sharma
2011 International SoC Design Conference, 298-301, 2011
Hardware Support to Improve Fuzzing Performance and Precision
R Ding, Y Kim, F Sang, W Xu, G Saileshwar, T Kim
28th ACM Conference on Computer and Communications Security (CCS), 2021
Practical Timing Side-Channel Attacks on Memory Compression
M Schwarzl, P Borrello, G Saileshwar, H Müller, M Schwarz, D Gruss
2023 IEEE Symposium on Security and Privacy (SP), 1186-1203, 2023
SQUIP: Exploiting the Scheduler Queue Contention Side Channel
S Gast, J Juffinger, M Schwarzl, G Saileshwar, A Kogler, S Franza, M Köstl, ...
2023 IEEE Symposium on Security and Privacy (SP), 2023
Hybrid mitigation of speculation based attacks based on program behavior
G Saileshwar, M Chowdhury
US Patent App. 16/681,642, 2021
PT-Guard: Integrity-Protected Page Tables to Defend Against Breakthrough Rowhammer Attacks
A Saxena, G Saileshwar, J Juffinger, A Kogler, D Gruss, M Qureshi
2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems …, 2023
Hardware support for low-cost memory safety
R Boivie, G Saileshwar, T Chen, B Segal, A Buyuktosunoglu
2021 51st Annual IEEE/IFIP International Conference on Dependable Systems …, 2021
The system can't perform the operation now. Try again later.
Articles 1–20